The present invention relates generally to memory chips, and more particularly to a systematic approach to fully specify the memory chip's behaviors.
A memory chip has a number of pins of various functions. For example, a conventional single-port static random access memory (SRAM) has a variety of pins, such as the synchronous clock (CLK) pin, chip-enable (CE) pin, read-write (WE) control pin, address (A) pin, and data input (D) pin. The CLK, CE, WE, A and D pins receive input signals that affect the memory chip's behaviors. It is desirable to provide an intellectual property (IP) library that specifies how the signal states of the pins affect the memory chip's behaviors.
A pin of a memory chip can be in a normal or abnormal state. The normal states include high and low signals, which usually represent logic “1” and “0,” respectively. The abnormal state includes exceptional states, such as unknown and high impedance states, and timing violation states. Conventionally, an IP library of a memory chip only specifies the normal states for the pins and their corresponding memory chip behaviors. Neither the exceptional nor the timing violation states are specified for the pins in the conventional IP library. This has certain drawbacks.
One of the drawbacks is the negative impression a customer may have on a memory chip provider. When the memory chip provider sells a memory chip to the customer, it usually comes with a specification of the memory chip behaviors. The customer who may be a circuit designer usually relies on the specification for designing his own products. In certain situations of circuit designs, the abnormal pin states and their corresponding memory chip's behaviors need to be specified. Because the conventional IP library of a memory chip does not provide information with respect to the abnormal states, the customer needs to specify those states on his own. Moreover, different customers may define the memory chip's behaviors differently. This creates undesirable confusion.
Another drawback of lacking the abnormal states specified in the conventional IP library of a memory chip is the confusion among the engineers of the chip provider. An IP library design process may involve various types of engineers, such as customer application engineers (CAE), computer aided design (CAD) engineers, design engineers and quality control (QC) engineers. A QC engineer may have different definitions for unspecified memory chip behaviors than a simulation model design engineer. This causes confusion when comparing the simulated modules with the memory chip's true behaviors.
Therefore, desirable in the art of memory designs are methods for systematically specifying pin states and defining their corresponding memory behaviors for a memory chip.